implementation using nand gates only pdf

Draw a single gate using AND-invert or invert-OR symbol for the sum term 4. Table 3.3: Truth Table AND gate using NAND gate 6. 1. Fig.4 Schematic of NAND Gate based PFD 2.2 NOR gate based PFD PFD using NOR gate is shown in figure.5. Table-4: Truth table Fig -8: NAND Gate IMPLIMENTATION OF MCCULLOCH PITTS MODEL: Fig -9: Architecture of NAND Gate Threshold value is 4 Net input is y in =x 1-x 2. All bubbles in the circuit should be paired so that they cancel out. • How a logic circuit implemented with AOI logic gates can be re-implemented using only NAND gates. Add an inverter at the first level for the term with a single literal F(x,y,z) = ∑(1,2,3,4,5,7) 3-24 Two-Level Implementation (NOR)! Implementation of AND using NAND A A.B B A 3. You can use NAND gate as universal gate. Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. 2. This gate can have minimum two inputs, output is always one. The truth table of the NAND gate must be understood by one before getting into the working of the circuit. using NAND or NOR gates only. In practice, constructing a digital circuit is cheapest by implementing it using only NAND gates, so I guess the idea is to show you how it's done. a. 2. store 0). To implement an INVERTER using NAND or NOR gates 4. 4. The NAND-based derivation of the OR gate is shown in Figure 1. For the breadboard part of this step, the blue wire represents Input 1 (A), wire... d) Implementation of NAND gate using 2 : 1 Mux. The other components we need are the LEDs and the 470Ω resistors in series with the LEDs to limit current to them so that they don't burn out. Step 2: Replace the AND gate with bubbled NOR gate(because of the alternate gate for AND gate is bubbled NOR) Step 3: Rearrange that bubbles to convert that logic into the corresponding alternate gates. Fan-in: it is the number of inputs that the gate is designed to have, the maximum inputs is 8 inputs per gate. They can be helpful in designing any complex logic circuit its implementation using NAND gates only. In this post you learn to use NAND as universal gate to create a logic diagram of a digital circuit with simple gates. Step 5: If any bubble is there extra then convert it into the NAND gate. 2. AND using NAND: Connect a NOT using NAND at the output of the NAND to invert it and get AND logic. NAND and NOR are universal gates Any function can be implemented using only NAND or only NOR gates. Step by step procedure to implement NOT gate by using only NAND gate. If both the inputs are high ie 1 than in that case only the output is low, otherwise if any of the input is high or if both the input is high the output will be high. Redraw the final circuit. 0). 4. A B C F 3. The values we will use for the pull down resistor is 10KΩ. Implementation Using Decoder If the number of minterms > 2 n /2 then express function as F’ and use NOR gate in the external gate to obtain the function F. If NAND gates are used to construct the decoder, then the external gate must be NAND gate (instead of OR gate) Procedure Part I 1. Draw a single AND-invert or invert-OR in the second level 4. D Latch 1. 2. Implementation of OR using NAND A A A.B = A+B B B Exercise. 3. And it has 2 outputs. The BORROW output The Map Method The complexity of the digital logic gates The complexity of the algebraic expression Logic minimization Algebraic approaches: lack specific rules The Karnaugh map A simple straight forward procedure A pictorial form of a truth table A diagram made up of squares Each square represents one minterm of the function that is to be Quartus software. Draw a bubble on each inversion bar. Write F’ in product of sums notation Solution 1: a) First draw the 2-level logic implementation directly from the Boolean equation. Write a simple sum-of-products expression for Z. Implement a 2-input XOR gate using only 2-input NAND gates. Learning Objectives. Identify and eliminate any double inversions (i.e., back-to-back inverters). b. 5. So its output is complement of the output of an AND gate. This carry bit from its previous stage is called carry-in bit. 4. We will use 2 pushbuttons as our inputs to the NAND gate. Figure 3: Gate-level implementation a) NAND/NOR gate, b) NOR/NAND gate tion should cost 14 transistors (6 transistors for the multi-plexer, 4 transistors for the NAND and 4 transistors for the NOR). The circuit consists of two resettable, edge triggered D flip flopswith their D inputs tied to logic 1 and a NOR Gate in the reset path. ... 1-Digital Logic.PDF Author: andy Created Date: So this gate is also called universal gate. Parrtt44::TTrrii--SSttaattee BBuuffffeerr: Implement 2-to-1 Multiplexer; see Figure 2, using only two tri-state buffers (others maxplus2 Tribuf ) and a single inverter on Quartus II (schematic). It takes binary input (0, 1) and gives binary output based on the input provided. Draw NAND gates for the first level 3. OR gate NAND implementation of OR gate 9. Step 4: Replace all gates with NAND gates or NOR gates depending on the type of implementation. Fig-4(d): XOR gate schematic diagram Using the instances of inverter, NAND gate and AND gate gates discussed above, master-slave D flip-flop is implemented as shown in fig.5. B(). • NAND-based ROM array . RESULT: The truth table of the above circuits is verified. Y = ~(a & b) & Fig. i. Implementation of AND using NAND A A.B B A 1. ü Realization of logic function using NOR gates Any logic function can be implemented using NOR gates. The interconnection of gates to perform a variety of logical operation is called logic design. Implementation of OR using NAND gate By putting additional inverters in the input we can achieve an OR gate by a NAND gate De Morgan's Law is the base of it. Typically, a logic IC will use either type as a basic building block, and repeat the gates as necessary. NAND and NOR are called universal gates as using only NAND or only NOR, any logic function can be implemented. TURTH TABLE. Finally, the circuit will be implemented physically on the breadboard by using only NAND gates and LED’s to represent the ouput. • Implementation using other gates (NAND and XOR) 2 2003 To be used with S. Dandamudi, “Fundamentals of Computer Organization and Design,” Springer, 2003. Basically each component, NOT, OR, AND, can each be made up of an assortment of NAND gates. (b) and (d) NAND and NOR gates can be used to realize all possible combinational logic functions. Using only nand gates. NAND and NOR are universal gates Any function can be implemented using only NAND or only NOR gates. Apparatus: logic trainer kit, NAND gates (IC 7400), wires. 3. Same two questions but use only 2-input NOR gates. 1 (a). Draw a NAND gate for each product term of the expression that has at least two literals. To see this, rst note that we can eliminate OR gates using De Mor-gan’s rule: OR(x 1;x 2) = NOT(AND(NOT(x 1);NOT(x 2))). NAND Function Implementation NAND gates can implement a simplified Sum-of-Products form. Redraw the network to remove as many of the internal inverter bubbles as possible using the hint shown in Fig. Subsequently using the instances of master-slave D flip-flop, AND gate and XOR gate the proposed synchronous 4-bit up counter is So its output is complement of the output of an AND gate. Simplify the function and express it in SOP form 2. This procedure produces a group of Using the NAND relationship, we have: G(A,B,C,D) = A B ⋅⋅⋅⋅C⋅⋅⋅⋅D = A B+C⋅⋅⋅⋅D The BORROW output Show how the simplified expression can be realised using 2-input NAND gates. SR Flip Flop with NAND Gate –ElectronicsHub.Org As we all know, logic Gate is a building block for the digital circuit. The output of a logic gate is ‘1’ when all its input are at logic 0.The gate is either (a) NAND or an EX OR gate Fill out the observation sheets, and submit them into Brightspace folder for Lab1a. RS latch implementation using A NOR gate. Since we only have the true literals available, we can create inverters by connecting the inputs 2. Once it is converted to POS, then it's very easy to implement using NOR gate. NOT using NAND: It’s simple. For NOR implementation, add Bubbles at the outputs of OR gates and at the inputs of AND gates. Draw a NAND gate for each product term 3. • Ex: NAND gate – Series nMOS: Y=0 when both inputs are 1 – Thus Y=1 when either input is 0 – Requires parallel pMOS • Rule of Conduction Complements – Pull-up network is complement of pull-down – Parallel -> series, series -> parallel 10 CMOS Logic Gates-1 Inverter Input Output a a V DD Gnd Pull-down Pull-up path path 2-input NAND Implementation and verification of Decoder/De-multiplexer and . 3. The NAND-based derivation of the AND gate is shown in Figure 1. For the breadboard part of this step, the blue wire represents Input 1 (A), wire... Therefore it is only necessary to implement a NAND or NOR gate in hardware to enable any logical function to be built. Popular Interview question on internet. 6. In the AOI implementation, identify and replace every AND,OR, and INVERTER gate with its NAND equivalent. 3. using NAND gates only, then we prove our point. (Proof for NAND gates) Any boolean function can be implemented using AND, OR and NOT gates. Step 1: implement using AND-OR logic. To implement a full adder using two half adders, the following expressions are used: Full-Adder using NAND gates Half-Subtractor: A Half-Subtractor is a combinational circuit that can be used to subtract one binary digit from another to produce a DIFFERENCE output and a BORROW output. 1. 2. They can be helpful in designing any complex logic circuit its implementation using NAND gates only. NAND Gate is a Universal Gate: (Proof for NAND gates) Any boolean function can be implemented using AND, OR and NOT gates. Record the result on table below. Output activation function is y= f (y in) = 1 if y in≥4 0 if y in <4. So you can do anything with just NAND gates. The circuits we have seen till now i.e., the Multiplexers, Demultiplexers, Encoders, Decoders, Parity Generators and Checkers and so on are known as Combinational Logic Circuits. How can we prove this? 31.2 NOR-based ROM Array . To identify a mystery chip Note: There is no lab report required for this lab. Now using the above as a starting point, design it using just NAND gates and inverters. NMOS only PMOS only PUN and PDN are dual networks. ... • Implement the complement of PDN X Y A B X = 0 if A = 1 or B = 1, i.e., A + B = 1 ... 4-input NAND Gate In1 In2 In3 In4 V DD GND Out ln2 ln1 ln2 Out ln1 ln4 ln3 ln3 ln4. Implementing an inverter using NAND gate . Prove that NOR is a universal gate. Prove that NOR is a universal gate. Here, each column consists of a pseudo-nMOS NOR gate driven by some of the row signals, i.e., the word line. Then we can eliminate AND gates in favor of NAND gates via AND(x 1;x 2) = NOT(NAND(x 1;x 2)). Simplify each function using a Karnaugh map and Sum of Products (SOP) representation (AND-OR). • Insert the appropriate IC into the IC base. 2. If the rest of the logic levels are applied it is observed that the truth table for an AND gate is realised. 3. Generic Static CMOS Gate V DD V Pullup network, connects output to DD, contains only PMOS IN1 V IN OUT 2 INn Pulldown network, connects output to GND, contains only NMOS For every set of input logic values, either pullup or pulldown network makes connection to VDD or GND • If both connected, power rails would be shorted together However, as the NAND/NOR gate is identical with an inverted majority function, it can be implemented using 10 transistors only (see Fig. RS latch implementation using A NOR gate SR latch have o two inputs S and R: S is called set and it is used to produce HIGH on Q (i.e. Table 3.4: Truth Table OR gate using NAND gate 8. Now, if Q = 0 and R = 1, then these are the states of inputs of gate B, therefore the outputs of gate B is at 1 (making it the inverse of Q i.e. To implement an OR gate using NAND gates Note: There is no lab report required for this lab. in in RESULTS: E. XOR GATE It is sometimes called as XOR gate or exclusive or gate. The boolean expression for output is as below [math]Y=\overline{\overline{(A\cdot\overline{(AB)})}\cdot\overline{(B\cdot\overline{(AB)})}}[/math] … Just connect both the inputs together. This is a graphical technique that utilizes a sum of product (SOP) form. The same applies for the OR gate implementation. OR using NAND: Connect two NOT using NANDs at the inputs of a NAND … If starting from a logic expression, implement the design with AOI logic.